This paper presents a 3.3-V, 18-bit sigma-delta modulator designed for digital audio. It has been simulated in a 0.6 _Ul1 double poly, triple metal CMOS process using poly-poly capacitors in all process corners and considering :t 10 % power supply voltage variations and -40°C to 85°C temperature range. The integral gain cocfficicnts of a 2-2 cascadcd sigma-delta modulator are realized to achieve a higher overload level factor that is needed for high-resolution noise limited performance modulators. The achieved overload level factor is -0.6 dBFS. This modulator samples at 6.4 MHz with OSR of 128 and Nyquist rate of 50 KHz. Simulation results give SNDR and DR of 110 dB and 1]4 dB, respectively, including the circuit noise. The total power consumption of the modulator including that of the output buffers, voltage buffers and clock generators is 80 mW.
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