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In this paper, we have a brief overview on advantages and disadvantages of dynamic logic design. To reduce the excessive power consumption of normal dynamic logic circuits, Data Driven Dynamic Logic or D3L is introduced. D3L also provides enhancements in reducing area and delay of a logic gate which has been confirmed by simulation results. Next, it is shown how different functions can be implemented in dynamic logic and then converted to an equivalent D3L design. To validate our simulation results, two 16-bit barrel shifters are implemented in an industrial 5-V, 0.6tm CMOS process: one in normal Domino logic and the other in our proposed D3L. Experimental measurements are in accordance with post-layout simulations and show that, depending on input patterns, a D3L shifter consumes 8% to 62% less power, and is 29% faster than the equivalent Domino circuit. In addition, it provides 9% area advantage over its Domino rival.